Applications of FPGAs in high-performance adaptive channel equalization
Ossif, Sergei (2016)
Ossif, Sergei
Metropolia Ammattikorkeakoulu
2016
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:amk-201602021833
https://urn.fi/URN:NBN:fi:amk-201602021833
Tiivistelmä
Wireless communications play an important role in today's society. To achieve higher speeds and bandwidth efficiency modulation techniques moved into the digital domain. The implementation relies on the use of digital signal processing to reduce intersymbol interference.
The idea of this project was to investigate the feasibility of building such system on FPGA platform. An implementation of Fractionally Spaced Equalizer using Least Mean Squares filters to configure 8-tap linear filters was built and evaluated. To test the system, the equalizer was connected to a microprocessor. The processor then fed the test sequence and calculated the time it takes to process the data. The results were then compared to a similar system built on DSP multicore processor system.
This implementation showed promising results. The system showed itself to be about 40 times faster than the DSP multicore processor system with an average time required to process 64 samples to be 13.7 us.
The idea of this project was to investigate the feasibility of building such system on FPGA platform. An implementation of Fractionally Spaced Equalizer using Least Mean Squares filters to configure 8-tap linear filters was built and evaluated. To test the system, the equalizer was connected to a microprocessor. The processor then fed the test sequence and calculated the time it takes to process the data. The results were then compared to a similar system built on DSP multicore processor system.
This implementation showed promising results. The system showed itself to be about 40 times faster than the DSP multicore processor system with an average time required to process 64 samples to be 13.7 us.